A full pin count (FPC) test is where a tester connects to all device pins of a semiconductor device which is generally used for probing or testing most semiconductor devices. However, for some digital system-on-a-chip (SOC) devices, such as advanced processors, that have a large gate counts (and thus large device pin counts such as 600 to 760 pins) for cost reasons a reduced pin count (RPC) test, where the tester only physically contacts a subset (e.g., 10%) of the device pins during the test, is generally used with the remaining device pins being untested.
Some devices for certain application however require stress conditions (higher than normal operating |voltage| and/or temperature) during probe or test. RPC does not allow imposing an electrical stress on the untested pins. For such devices (e.g., SOC processors) needing electrical stress during test, there is thus a significant challenge moving to in-situ burn-in because the FPC test needed to stress all pins results in a low test throughput. Another option is split testing (the combination of RPC and FPC) which can be implemented to improve multisite efficiency and throughput (ultimately the cost of test) as compared to 100% FPC, but this testing combination does not electrically stress all the device pins.